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HS-2510RH
TM
Data Sheet
August 1999
FN3592.2
Radiation Hardened High Slew Rate Operational Amplifier
The HS-2510RH is a radiation hardened high performance operational amplifier which set the standard for maximum slew rate and wide bandwidth operation in moderately powered, internally compensated, monolithic devices. In addition to excellent dynamic characteristics, this dielectrically isolated amplifier also offers low offset current and high input impedance. The 50V/ms minimum slew rate and fast settling time of the HS-2510RH are ideally suited for high speed D/A, A/D, and pulse amplification designs. The HS-2510RH superior bandwidth and 750kHz minimum full power bandwidth are extremely useful in RF and video applications. To insure compliance with slew rate and transient response specifications, all devices are 100% tested for AC performance characteristics over full temperature limits. To improve signal conditioning accuracy, the HS-2510RH provides a maximum offset current of 25nA and a minimum input impedance of 50M, both at 25oC, as well as offset voltage trim capability. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95686. A "hot-link" is provided on our homepage for downloading.
Features
* Electrically Screened to SMD # 5962-95686 * QML Qualified per MIL-PRF-38535 Requirements * High Slew Rate . . . . . . . . . . . 50V/s (Min), 65V/s (Typ) * Wide Power Bandwidth . . . . . . . . . . . . . . . . 750kHz (Min) * Low Offset Current . . . . . . . . . . . . 25nA (Min), 10nA (Typ) * High Input Impedance . . . . . . . 50M (Min), 100M (Typ) * Wide Small Signal Bandwidth . . . . . . . . . . . 12MHz (Typ) * Fast Settling Time (0.1% of 10V Step). . . . . . 250ns (Typ) * Low Quiescent Supply Current . . . . . . . . . . . . 6mA (Max) * Internally Compensated For Unity Gain Stability * Total Gamma Dose . . . . . . . . . . . . . . . . . . . . 10kRAD(Si)
Applications
* Data Acquisition Systems * RF Amplifiers * Video Amplifiers * Signal Generators * Pulse Amplification
Ordering Information
ORDERING NUMBER 5962D9568601VPA 5962D9568601VPC 5962D9568601VXC INTERNAL MKT. NUMBER HS7-2510RH-Q HS7B-2510RH-Q HS9-2510RH-Q TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125
Pinouts
HS-2510RH GDIP1-T8 (CERDIP) OR HS-2510RH CDIP2-T8 (SBDIP) TOP VIEW HS-2510RH CDFP3-F14 (FLATPACK) TOP VIEW
NC 1 BAL ININ+ V1 2 3 4 8 COMP V+ OUT BAL COMP 2 BAL 3 IN- 4 IN+ 5 NC 6 NC 7 14 NC 13 V+ 12 OUT
+
-
7 6 5
+
-
11 BAL 10 V9 NC 8 NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
HS-2510RH Test Circuit
ACOUT V1 0.1 100K 1 OPEN 2 S3A S1 OPEN 2 S2 1 1 1 2 S5A 1 S7 3 BAL ADJ OPEN 1 2 2 S5B 1 S8 OPEN 2 1 2 S9 2 V2 10K BUFFER 500K OPEN 3 1 + 2K 50pF (NOTE 1) FOR LOOP STABILITY, USE MIN VALUE CAPACITOR TO PREVENT OSCILLATION 50K -1 +
+VCC
-1/10
DUT +
-
-
1 S6
OPEN 2 100K 2 S3B 100 1 OPEN 100
2K VAC 0.1 1K 1 -VEE
x2 5K 2 S4 50K 1
EOUT
ALL RESISTORS = 1% () ALL CAPACITORS = 10% (F)
NOTE: 1. Includes stray capacitances. FIGURE 1. SIMPLIFIED TEST CIRCUIT
Test Circuit and Waveforms
+15V INPUT + 1K
OUTPUT
-
2K
50pF
-15V
FIGURE 2. SIMPLIFIED TEST CIRCUIT
+5V INPUT INPUT 0V OVERSHOOT 90% OUTPUT 10% -5V T SLEW RATE = V/T V 90% OUTPUT 10% -200mV +200mV 0V
-5V +5V
RISE TIME
NOTE: Measured on both positive and negative transitions. Capacitance at Compensation pin should be minimized. FIGURE 3. SLEW RATE WAVEFORM
NOTE: Measured on both positive and negative transitions. Capacitance at Compensation pin should be minimized. FIGURE 4. TRANSIENT RESPONSE WAVEFORM
2
HS-2510RH Typical Performance Curves
100 80 60 40 20 OFFSET CURRENT 0 -20 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) GAIN (dB)
Unless Otherwise Specified: TA = 25oC, VSUPPLY = 15V
90
BIAS CURRENT 85 VS = 20V 80 VS = 15 VS = 10
CURRENT (nA)
75 -50 -55 -25 0 25 50 75 100 125 TEMPERATURE (oC)
FIGURE 5. INPUT BIAS AND OFFSET CURRENT vs TEMPERATURE
FIGURE 6. OPEN LOOP VOLTAGE GAIN vs TEMPERATURE
100 NORMALIZED PARAMETERS REFERRED TO VALUES AT 15V EQUIVALENT INPUT NOISE (V)
1.1 SLEW RATE
10
10K SOURCE RESISTANCE 0 SOURCE RESISTANCE
1.0 BANDWIDTH
BANDWIDTH
1.0
0.9
SLEW RATE
THERMAL NOISE OF 10K RESISTOR 0.1 100Hz 1kHz 10kHz 100kHz 1MHz
0.8 10V 15V SUPPLY VOLTAGE 20V
UPPER 3dB FREQUENCY LOWER 3dB FREQUENCY (10Hz)
FIGURE 7. EQUIVALENT INPUT NOISE vs BANDWIDTH
FIGURE 8. NORMALIZED AC PARAMETERS vs SUPPLY VOLTAGE AT 25oC
1.1 NORMALIZED PARAMETERS REFERRED TO VALUES AT 25C PEAK-TO-PEAK VOLTAGE SWING BANDWIDTH SLEW RATE 1.0 SLEW RATE
35 30 25 20 15 10 5 0 10K
VS = 20
VS = 15
BANDWIDTH 0.9
VS = 10
0.8 -50 -55 -25 0 25 50 75 100 125 TEMPERATURE (oC)
100K
1MEG FREQUENCY (Hz)
10MEG
FIGURE 9. NORMALIZED AC PARAMETERS vs TEMPERATURE
FIGURE 10. OUTPUT VOLTAGE SWING vs FREQUENCY AT 25oC
3
HS-2510RH Typical Performance Curves
120 OPEN-LOOP VOLTAGE GAIN (dB) 100 80 60 40 20 0 -20 10 100 1K 10K 100K 1M 10M 100M FREQUENCY (Hz) 300pF 1000pF 100pF 0pF 30pF CURRENT (mA) 4.0 3.8 3.6 3.4 3.2 -50 -55 -25 0 25 50 75 100 125 TEMPERATURE (oC)
Unless Otherwise Specified: TA = 25oC, VSUPPLY = 15V (Continued)
4.4 4.2 VS = 20 VS = 15 VS = 10
NOTE: External compensation components are not required for stability, but may be added to reduce bandwidth, if desired. FIGURE 11. OPEN LOOP FREQUENCY RESPONSE FOR VARIOUS VALUES OF CAPACITORS FROM COMPENSATION PIN TO GROUND
120 OPEN LOOP VOLTAGE GAIN (dB) 100 80 PHASE 60 40 20 0 -20 10 100 1K 10K 100K 1M 10M 100M FREQUENCY (Hz) 90o 120o 150o 180o 30o 60o PHASE ANGLE RT V+
FIGURE 12. POWER SUPPLY CURRENT vs TEMPERATURE
20k
IN
BAL
OUT
GAIN
V-
NOTE: Tested offset adjustment is |VOS + 1mV| minimum referred to output typical range is 8mV for RT = 20k. FIGURE 14. SUGGESTED VOS ADJUSTMENT
FIGURE 13. OPEN LOOP GAIN AND PHASE RESPONSE vs FREQUENCY
1000 INPUT NOISE VOLTAGE (nV/Hz) INPUT NOISE VOLTAGE
100 INPUT NOISE CURRENT (pA/Hz)
100
10
INPUT NOISE CURRENT 10 1
1 1 10 100 1K 10K FREQUENCY (Hz)
0.1 100K
FIGURE 15. INPUT NOISE DENSITY vs FREQUENCY
4
HS-2510RH Burn-In Circuits
HS7-2510RH CERDIP HS9-2510RH CERAMIC FLATPACK
1 2 R1 3 VD2 4 C2 +
8 7 6 C3 5 C1 D1 V+ 1 2 3 4 5 R1 6 7 9 8 14 13 12 11 10 C2 D2 VC3 C1 D1 V+
NOTES: 2. R1 = 1M, 5%, 1/4W (Min) 3. C1 = C2 = 0.01F/Socket (Min) or 0.1F/Row (Min) 4. C3 = 0.01F/Socket (10%) 5. D1 = D2 = 1N4002 or Equivalent (Per Board) 6. |(V+) - (V-)| = 30V
NOTES: 7. R1 = 1M, 5%, 1/4W (Min) 8. C1 = C2 = 0.01F/Socket (Min) or 0.1F/Row (Min) 9. C3 = 0.01F/Socket (10%) 10. D1 = D2 = 1N4002 or Equivalent (Per Board) 11. |(V+) - (V-)| = 31V 1V
Irradiation Circuit
HS7-2510RH
C 1 2 R 3 V2 C 4 6 5 8 7 C V1
NOTES: 12. V1 = +15V 10% 13. V2 = -15V 10% 14. R = 1M 5% 15. C = 0.1F 10%
5
HS-2510RH Schematic Diagram
OFFSET OFFSET
V+ R5 200 R6 200 R9 200 R8 200 R11 2K R7 1.8K Q2 R1 4K R2 2K Q5 R3 960 Q4 COMP R4 11.13K INPUT+ Q37 Q38 Q35 Q29 1.68K R25 1.68K R26 Q28 Q26 Q34 Q33 Q32 INPUTQ36 R22 240 Q30 Q31 R23 3K Q27 R20 3K Q25 Q20 Q24 R18 1.48K Q23 R17 1.48K Q22 Q21 R16 1.48K R15 740 VQ39 Q40 Q19 R19 6.3K Q13 Q12 Q17 Q15 Q7 Q9 Q6 R10 1.8K Q8 Q10 C2 2.7pF R12 1.1K Q16 C1 10pF R13 30 Q11 Q14 R14 30 Q18 OUTPUT
Q1
Q3
6
HS-2510RH Die Characteristics
DIE DIMENSIONS: 65 mils x 57 mils x 19 mils (1660m x 1950m x 483m) INTERFACE MATERIALS: Glassivation: Type: Nitride Thickness: 7kA 0.7kA Top Metallization: Type: Aluminum Thickness: 16kA 2kA Substrate: Linear Bipolar, DI Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential (Powered Up): Unbiased ADDITIONAL INFORMATION: Worst Case Current Density: <2 x 105A/cm2 Transistor Count: 40 Die Attach: Temperature: CERDIP 460oC (Max)
Metallization Mask Layout
HS-2510RH
V+ OUT BAL
V-
COMP
BAL
-IN
+IN
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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